Asia Silicon Valley

Development of Ultra High-Speed SerDes ICs

Principal Investigator:Jri Lee, Ph.D. of National Taiwan University


This project will integrate and optimize the achievements accumulated by Professor Jri Lee’s group including exist knowledge property, research energy, as well as the combination of the supply chain. We aim to develop a cutting-edge communication IC company. We will focus on the next-generation SerDes communication ICs including optical links (400G Ethernet)/ backbone networks/ super large cloud computing center, and the widely-used application of over 25Gbps(PCI-E Gen 5, USB 4.0 etc.) Mainly on the special circuits developed, our group will be in the progress of SerDes ICs in 28 nm and 16 nm CMOS technology, expecting to propose the first standardized 112Gbps SerDes IC. In the commercial aspect, we have gradually build up the cooperation relationship with foreign large system manufacturers, hoping to introduce products into the market in the short time. If this project is approved, we will build up a solid, stable and large-scale company with highest efficiency of fund reimbursement, the shortest development schedule, and the biggest market plan.  

1learn more
Team Introduction

Our team is with Professor Lee as the core, and the core value of the team is to launch world-class and high-order Chip-to-Chip technology. Our team have an edge on having a place once at one of the top conference in the world; moreover, the R&D results from the team have been published more than 30 papers at one of the top conference in the world and journal papers. Also, we have many completely cooperative experiences with the world-class companies.

Jri Lee (S’03-M’04) received the B.Sc. degree in electrical engineering from National Taiwan University (NTU), Taipei, Taiwan in 1995, and the M.S. and Ph.D. degrees in electrical engineering from the University of California, Los Angeles (UCLA), both in 2003. His current research interests include high-speed wireless and wireline transceivers, phase-locked loops, and data converters. Professor Lee has ever received ISSCC Beatrice Winner Award for Editorial Excellence(2007), ISSCC Takuo Sugano Award for Outstanding Far-East Paper(2008), and etc.

Pen-Jui Peng received the Ph.D. degree in electrical engineering from National Taiwan University (NTU), Taipei, Taiwan in 2014. He has more than ten years of R&D experience, and he has ever received Finalist of Best Student Paper, Radio Frequency Integrated Circuit (RFIC) Conference.

The team members are all M.S. or Ph.D. degree in National Taiwan University (NTU). All of them have solid IC design experience.

Goals and Plan

This proposal is about using 28nm to achieve higher specifications of more than 100Gb/s in single channel. Respectively proceed with 112Gb/s single PAM8 Chipset and 4x25Gb/s NRZ optical communication TX chipset. The steps are listed below:

Entry Barrier

The market segmentation variable has innovative circuit development and system integration capabilities: We have published dozens of paper at one of the top conference in the world and journal papers, and more than ten patent at home and abroad. Also, our team has ever received many paper awards which are important and high-profile in the world (e.g. ISSCC Best Paper Award). The development team, which is complete and strong, has undertaken the domestic and international first-tier manufacturer’s project about the development of ASIC, and being well received. The design thinking and technical level have already been departed from the laboratory stage and entered the actual product category. The host familiar with the industrial ecology and has a good relationship with domestic and foreign companies. It helps to obtain resources and actively seek listings or mergers and acquisitions in the future. Target market selection in the past 30 years, wireline communication has been developing steadily and continuously. Due to the acceleration of cloud computing, artificial intelligence, big data, etc., the communication capacity of the Internet era is growing faster. The high-end communication chip is a battlefield for IC Design companies. The product market positioning will focus on providing high specification communications IP and chip sales, model block or barebone sample and solutions. The target customer is locked into an optical communication system factory or other major system factory.

Market Scope

The market size and trend of SerDes has grown from 10G, 28G to the current 56G specifications in the past 10 years, and the industry scale has grown by more than 20% per year. In the future, 112G specifications will show stronger and more sustainable growth in applications such as ultra-large data centers, ultra-high-performance switches, and 4G/5G infrastructure. Predicting market share in the next 3-5 years, the backbone network will flourish, and we will complete the channel with our partners and start from the lower-order circuits to gradually occupy the market.

Video Introduction